Technical Features

RDL Resolution @Line Width: 3 μm; Via: 6 μm
RDL Stacking: 3 Layers (Double Side)
Warpage: < 0.3 mm @G2.5 (with EMC)
Cu Pillar Size: 150 μm; Height: 90 μm
Glass Substrate Size: 370 X 470 mm² (G2.5)

Technical Description

To meet the future demands of high-speed IC computing, a low-warp, high-resolution panel-level packaging (PLP) double-sided RDL (Redistribution Layer) technology is being developed. Based on the existing single-sided process flows used by packaging and panel manufacturers, a large-size, low-warp double-sided RDL (37 x 47 cm²) is being created, incorporating panel-level copper pillar processes to electrically connect the upper and lower RDL layers. Additionally, high-resolution circuitry (3 μm) can also be applied to chip-first IC packaging for chip displacement compensation within the RDL, making it suitable for panel-level interposers required in advanced packaging technologies.

Photos